Integrated circuits are made up of millions of active devices formed in or on a substrate, such as a silicon wafer. The active devices are chemically and physically connected into a substrate and are interconnected through the use of multilevel interconnects to form functional circuits. In one manufacturing process, a dielectric substrate is patterned by a conventional dry etch process to form holes and trenches for vertical and horizontal interconnects. The patterned surface is then optionally coated with a diffusion barrier layer and/or an adhesion-promoting layer, followed by deposition of a metal layer to fill the trenches and holes. Chemical-mechanical polishing (CMP) is employed to reduce the thickness of the metal layer, as well as the thickness of the diffusion barrier layer and/or adhesion-promoting layer, until the underlying dielectric layer is exposed, thereby forming the circuit device.
One way to fabricate planar metal circuit traces on a silicon dioxide substrate is referred to as the damascene process. In accordance with this process, the silicon dioxide dielectric surface having optionally a layer of silicon nitride deposited thereon is patterned by applying a photoresist, exposing the photoresist to irradiation through a pattern to define trenches and/or vias, and then using a conventional dry etch process to form holes and trenches for vertical and horizontal interconnects. The silicon nitride functions as a “hard mask” to protect the silicon dioxide surface that is not part of the trenches and/or vias from damage during etching. The patterned surface is coated with an adhesion-promoting layer such as titanium or tantalum and/or a diffusion barrier layer such as titanium nitride or tantalum nitride. The adhesion-promoting layer and/or the diffusion barrier layer are then over-coated with a metal layer. Chemical-mechanical polishing is employed to reduce the thickness of the metal over-layer, as well as the thickness of any adhesion-promoting layer and/or diffusion barrier layer, until a planar surface that exposes elevated portions of the silicon nitride surface is obtained. The vias and trenches remain filled with electrically conductive metal forming the circuit interconnects.
Tungsten and copper have been increasingly used as the electrically conductive metal. However, aluminum, which has been used in earlier generation processes to fabricate circuit interconnects via subtractive processes such as etching techniques, is now under consideration for use in damascene processes. The combination of aluminum and titanium offers potentially lower resistivity than other metal/barrier layer combinations, with corresponding potential improvement in circuit performance. However, compositions useful in the chemical-mechanical polishing of aluminum typically exhibit considerably lower removal rates in the polishing of underlying titanium. Thus, use of such polishing compositions in aluminum damascene fabrication processes to polish aluminum as well as titanium require overpolishing of aluminum remaining in circuit lines, resulting in considerable dishing of the lines. Thus, there remains in the art a need for improved compositions and methods for the chemical-mechanical polishing of substrates comprising aluminum as a conducting material and titanium as a barrier material.